1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of both reducing short channel effects and reducing junction capacitance in the fabrication of integrated circuits.
2. Description of the Prior Art
In the fabrication of integrated circuit devices, typically heavily doped source and drain regions are formed in the semiconductor substrate after formation of the gate electrode. Lightly doped regions are normally formed in the substrate immediately adjacent to the region under the gate electrode. Halos are normally used to suppress n-channel and p-channel short channel effects. When the channel length is sufficiently short, source to drain punchthrough can be caused by drain-induced-barrier-lowering (DIBL). A halo is a pocket implant to suppress the DIBL. The halo is implanted with opposite dosage to the lightly doped source and drain implant (LDD). The halo implant is deeper both vertically and laterally than the LDD. This effectively suppresses the high electrical field regions causing punchthrough. A prior art halo implant is illustrated in FIG. 1. A polycide gate 52 has been formed over a semiconductor substrate 10. Heavily doped source and drain regions 54 and lightly doped source and drain regions 56 have been implanted. The p- halo implant 58 is illustrated.
Halos have disadvantages. By effectively increasing the well concentration at the junction boundary, the halo increases the junction capacitance. This leads to heavier loading which slows down the circuit. It is desirable to provide a process to form a halo only in the small critical region so that junction capacitance and circuit speed are not effected.
U.S. Pat. Nos. 4,757,026 to Woo et al and 5,032,535 to Kamijo et al use disposable spacers in implanting lightly doped regions.